(1) Field of the Invention
This invention relates to a semiconductor memory and, more particularly, to a semiconductor memory having a memory core for dynamically holding data.
(2) Description of the Related Art
Pseudostatic RAMs (PSRAMs) are semiconductor memories, in which a dynamic RAM (DRAM) core is used as a memory core (cell) and which have a static RAM (SRAM) interface.
Memory cores in PSRAMs have a DRAM structure. PSRAMs therefore can be fabricated at low cost compared with SRAMs. Unlike memory cores in SRAMs, however, memory cores in DRAMs can hold data only for a limited period of time and need the operation of rewriting data, which is called refresh. Moreover, because of destructive read out, special care is necessary to control memory cores in DRAMs. With SRAMs, such special care isunnecessary. With conventional PSRAMs, it has been difficult to reconcile all of this care with compatibility with SRAM interfaces. Accordingly, unlike ordinary SRAMs, various operational restrictions have been placed on PSRAMs. Though PSRAMs can be fabricated at low cost, these restrictions limit their use and they are not useful for users and manufacturers. Therefore, it is necessary to realize PSRAMs having an SRAM compatible interface by removing these restrictions.
Products which bear FCRAM (registered trademark) are PSRAMs. Specifications for FCRAMs include restrictions which are not placed on ordinary SRAMs. For example, when an FCRAM is in a standby state (a state in which data cannot be read or written, that is to say, an inactive state), predetermined voltages must be inputted to address terminals and control terminals, such as chip enable terminals and read/write terminals.
With ordinary SRAMs, only voltages to be inputted to chip enable terminals are specified and voltages to be inputted to the other terminals are not specified.
As stated above, the restriction has been placed on PSRAMs. That is to say, at standby time voltages must be inputted from the outside. To remove this restriction, a circuit for holding a predetermined signal (voltage) state and outputting it to the inside should be included. FIG. 7 is a view showing the circuit structure of a conventional PSRAM. As shown in FIG. 7, a PSRAM includes buffer circuits 61a through 61n, buffer circuits 62a through 62n, terminals /CE1 and CE2 and terminals /WE through /LB, being control terminals, terminals A0 through An, being address terminals, and an OR circuit Z2.
The buffer circuits 61a and 61b amplify signals inputted to the terminals /CE1 and CE2, respectively, so that they can drive circuits in the PSRAM.
The buffer circuits 61c through 61n amplify signals inputted to the terminals /WE through /LB, respectively, according to the state of signals inputted to the buffer circuits 61a and 61b (according to the state of a signal outputted from the OR circuit Z2) so that they can drive circuits in the PSRAM. When a signal outputted from the OR circuit Z2 is in the “L” state, the buffer circuits 62a through 62n amplify signals inputted to the terminals A0 through An respectively.
A signal for putting the PSRAM into a standby (inactive) state or a nonstandby (active) state is inputted to the terminal /CE1 or CE2. When a signal in the “H” state is inputted to the terminal /CE1 or when a signal in the “L” state is inputted to the terminal CE2, the PSRAM will go into a standby state.
A signal for controlling the reading or writing of data is inputted to the terminal /WE. When a signal in the “L” state is inputted to the terminal /WE, the PSRAM will go into a state in which data can be written thereto. When a signal in the “H” state is inputted to the terminal /WE, the PSRAM will output data it stores.
A signal for controlling the width of outputted (read) data (for exercising byte control) is inputted to the terminal /LB. For example, when a signal in the “L” state is inputted to the terminal /LB, only the eight low order bits of data will be outputted.
(Write) address signals for writing data and (read) address signals for reading data are inputted to the terminals A0 through An.
The OR circuit Z2 performs an OR operation on signals outputted from the buffer circuits 61a and 61b and outputs a result to the buffer circuits 61c through 61n and the buffer circuits 62a through 62n. When a signal in the “L” state is inputted from the buffer circuit 61a and a signal in the “H” state is inputted from the buffer circuit 61b (when the PSRAM is in a nonstandby state), the OR circuit Z2 will output a signal in the “L” state.
When a signal in the “H” state is inputted to the terminal /CE1 or a signal in the “L” state is inputted to the terminal CE2, the PSRAM will go into a standby state. At this time the PSRAM will not read or write data even when a signal in the “H” or “L” state is inputted to the terminal /WE. The reason for this is that a signal in the “H” state is outputted from the OR circuit Z2 and that the buffer circuits 61c through 61n and the buffer circuits 62a through 62n will not amplify a signal.
When a signal in the “L” state is inputted to the terminal /CE1 and a signal in the “H” state is inputted to the terminal CE2, the PSRAM will go into a nonstandby state. A signal in the “L” state is outputted from the OR circuit Z2 and the buffer circuits 61c through 61n and the buffer circuits 62a through 62n will go into an amplifiable state. Then the PSRAM will read or write data when a signal in the “H” or “L” state is inputted to the terminal /WE. The PSRAM will read data from or write data to an address indicated by address signals which are being inputted to the terminals A0 through An.
FIG. 8 is a circuit diagram showing the details of the buffer circuits. As shown in FIG. 8, the buffer circuit 61a includes transistors Q15 and Q17, being p-channel MOS transistors, and transistors Q16 and Q18, being n-channel MOS transistors. The transistors Q15 and Q16 make up an inverter circuit. The transistors Q17 and Q18 also make up an inverter circuit. The structure of the buffer circuit 61b is the same as that of the buffer circuit 61a, so a detailed description of it will be omitted.
The buffer circuit 61c includes transistors Q23, Q24 and Q27, being p-channel MOS transistors, and transistors Q25, Q26 and Q28, being n-channel MOS transistors. The transistors Q24 and Q25 make up an inverter circuit. The transistors Q27 and Q28 also make up an inverter circuit. When a signal in the “L” state is inputted from the OR circuit Z2, the transistor Q23 supplies power supply voltage Vdd to the inverter circuit made up of the transistors Q24 and Q25 and puts it into an operable state. When a signal in the “H” state is inputted from the OR circuit Z2, the transistor Q26 outputs ground voltage (a signal in the “L” state) to the inverter circuit made up of the transistors Q27 and Q28. The structure of the buffer circuits 61d through 61n and the buffer circuits 62a through 62n (not shown) is the same as that of the buffer circuit 61c. 
That is to say, when the PSRAM is in a standby state, a signal kept in the “H” state will be outputted from the buffer circuits 61c through 61n and the buffer circuits 62a through 62n to the inside of the PSRAM regardless of the state of signals which are being inputted to the terminals /WE through /LB, being control terminals, and the terminals A0 through An, being address terminals. As a result, it is unnecessary to input voltage to the control terminals and the address terminals at the time of the PSRAM being in a standby state. Therefore, a PSRAM, which is not subject to the above restriction and which has an SRAM compatible interface, can be realized.
By the way, semiconductor integrated circuits in which a buffer circuit is used include the one comprising a detection circuit for detecting whether an external control signal clock is functioning and an input buffer for accepting an external control signal clock and outputting an internal control signal on the basis of the result of detection by the detection circuit (see, for example, Japanese Unexamined Patent Publication No. 11-317076, pp. 2-3 and FIG. 1).
A signal inputted to the terminal /CE1 is inputted to the buffer circuits 61c through 61n and the buffer circuits 62a through 62n via the buffer circuit 61a and the OR circuit Z2. A signal inputted to the terminal CE2 is inputted to the buffer circuits 61c through 61n and the buffer circuits 62a through 62n via the buffer circuit 61b and the OR circuit Z2. A signal inputted to the terminal /CE1 is delayed by the buffer circuit 61a and the OR circuit Z2 and is outputted to the buffer circuits 61c through 61n and the buffer circuits 62a through 62n. A signal inputted to the terminal CE2 is delayed by the buffer circuit 61b and the OR circuit Z2 and is outputted to the buffer circuits 61c through 61n and the buffer circuits 62a through 62n. Therefore, a signal, which is being inputted to the terminal /WE and which is amplified and outputted by the buffer circuit 61c, will be delayed. This signal will also be delayed by the buffer circuit 61c itself. Actually, this signal will be delayed further not only by transistors but also by, for example, a delay element (not shown) inserted to filter a signal glitch and the like.
FIG. 9 is a view showing timing inside the PSRAM. A waveform C1 shown in FIG. 9 indicates the waveform of a signal which is being inputted to the terminal /CE1. A waveform C2 indicates the waveform of a signal which is being inputted to the terminal CE2. A waveform C3 indicates the waveform of a signal which is being inputted to the terminal /WE. A waveform C4 indicates the waveform of a signal which is being outputted from the OR circuit Z2. A waveform C5 indicates the waveform of a signal outputted from the buffer circuit 61c. 
As shown by the waveforms C1 and C2, it is assumed that the signal in the “H” state is inputted to the terminal /CE1 and that the signal in the “H” state is inputted to the terminal CE2 (the PSRAM is in a standby state). As shown by the waveform C4, the transition of the state of the signal outputted from the OR circuit Z2 will lag behind the transition of the state of the signal inputted to the terminal /CE1 by the buffer circuits 61a and 61b and the OR circuit Z2. Moreover, as shown by the waveform C5, the transition of the state of the signal outputted from the buffer circuit 61c will be delayed by the buffer circuit 61c itself.
As shown by the waveform C3, a signal in the “L” state for writing data is being inputted to the terminal /WE when the PSRAM makes the transition from a standby state to a nonstandby state (when the signal which is being inputted to the terminal /CE1 makes the transition to the “L” state). As shown by the waveform C5, then the signal in the “L” state is outputted to the inside of the PSRAM after some delay.
When the PSRAM makes the transition from a standby state to a nonstandby state, the operation of writing data is being performed outside the PSRAM. Inside the PSRAM, however, read operation will be performed because of a signal delay as shown by the waveform C5. This will cause a data collision.